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128Mb: x16 Mobile SDRAM
Operation
except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the
inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must
remain LOW.
During self refresh, the device is refreshed as identified in the extended mode register
(see PASR setting). The SDRAM must remain in self refresh mode for a minimum period
equal to t RAS and may remain in self refresh mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for t XSR because time is
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands should be issued at
once and then every 15.625μs or less, as both SELF REFRESH and AUTO REFRESH
utilize the row refresh counter.
Deep Power-Down
Deep power-down is an operating mode used to achieve maximum power reduction by
eliminating the power to the memory array. Data will not be retained once the device
enters deep power-down mode.
This mode is entered by having all banks idle then CS# and WE# held LOW with RAS#
and CAS# held HIGH at the rising edge of the clock, while CKE is LOW. This mode is
exited by asserting CKE HIGH.
Operation
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 7 on page 18).
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the t RCD specification. t RCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a t RCD specification of 20ns with a 125 MHz clock (8ns period)
results in 2.5 clocks, rounded to 3. This is reflected in Figure 8 on page 18, which covers
any case where 2 < t RCD (MIN)/ t CK ≤ 3. (The same procedure is used to convert other
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by t RC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE commands to different banks is
defined by t RRD.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
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